1. Field of the Invention
This invention relates to a computer system and a method for setting a recovery time.
2. Description of the Related Art
Recently, with the development of semiconductor technology, the cost of microprocessors, memories, and peripheral control LSIs has become extremely lowered. Computer systems with relatively high performance can be constructed by combining ICs via system buses. As it has been strongly demanded to enhance the operation rate of such computer systems, the operation rate of the microprocessor which is the nucleus of the computer system, is made even higher and the function thereof tends to be further enhanced. The high operation rate of the computer system can be attained by effecting the processes of the microprocessor in a pipeline fashion, using a cache memory, a write buffer, or the like as well as by enhancing the operation rate of the microprocessor itself.
However, peripheral LSIs were developed after the microprocessor was developed. Because there are many kinds of LSIs, it takes a longer time to develop such LSIs. Therefore, the operation rate of peripherals LSIs have not been significantly improved. Most of the hardware optional cards and application softwares are designed to function on conventional computer systems with an operation rate which is relatively low and which cannot respond to the high rate access.
As described above, a computer system is required to attain the high rate operation, and at the same time, the computer system is required to maintain compatibility with a conventional computer system. That is, when a high rate computer system is newly developed, it is required to support not only hardware devices and application softwares which are designed for the developed computer systems having an operation rate of the same level, but also hardware optional cards and application software which have been designed to function on the conventional computer systems with an operation rate which is relatively low.
When input/output (I/0) commands are successively executed for low operation rate hardware, the hardware cannot respond to the commands and an error occurs. Therefore, in the prior art, in order to obtain a recovery time upon execution of an I/0 command, one or more dummy jump commands (JMP), as shown in FIG. 1A, or a dummy loop, as shown in FIG. 1B, is inserted into the program including the I/0 commands.
However, in a case where the operation clock frequency of the microprocessor becomes high and pipeline processing is used, the dummy jump command or dummy loop will be completed in a moment. In this case, a sufficiently long recovery time cannot be attained.